1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a nonvolatile semiconductor memory device using a high potential input.
2. Description of the Related Art
A conventional nonvolatile semiconductor memory device such as an EPROM (ultraviolet erasable programmable read only memory) or EEPROM (electrically erasable programmable read only memory) has a power source terminal (V.sub.PP power source terminal) for receiving a high potential V.sub.PP for programming. The V.sub.PP power source terminal is also used to receive another signal input.
When data is programmed into an EPROM, an internal high potential detection circuit is set into operative state by applying a high potential signal for tri-state control to a part of address terminals, for example, an input terminal for an address signal A9, so that a code called an electric signature indicating the name of the maker and the name of the device is read from the EPROM. An EPROM writer reads the signature code from the EPROM and automatically specifies the EPROM, and automatically sets the condition of writing data into the device without fail. As the potentials of tri-state control, a logical low level, a logical high level and a high potential V.sub.H sufficiently higher than the logical high level ar generally used.
FIG. 1 shows an example of an input-first stage circuit connected to a V.sub.PP power source terminal 31 in the conventional EPROM. In the above input-first stage circuit, a 2-input NOR circuit 32 of CMOS (complementary insulated gate) structure is constructed by P-channel MOS (insulated gate) transistors P1 and P2 and N-channel MOS transistors N1 and N2. Two-stage amplifying inverters 33 and 34 are connected to the output stage of the NOR circuit 32. A multiplexed signal of the V.sub.PP voltage and control signal BYTE is input through the V.sub.PP power source terminal 31 as one input of the NOR circuit 32 and a chip enable control signal CE* is input as the other input of the same. The V.sub.PP power source terminal 31 is supplied with a control signal BYTE of "L" level (Vss potential, for example, 0 V) or "H" level (Vcc potential, for example, 5 V) in the read mode and supplied with a V.sub.PP voltage in the program mode. The control signal BYTE selectively sets the 8-bit read operation or 16-bit read operation.
In the mode in which a programming high potential V.sub.PP is not input to the V.sub.PP power source terminal 31, such as the read mode of the EPROM of the circuit shown in FIG. 1, when the control signal BYTE or chip enable control signal CE* is set at the "H" level, the N-channel transistor N1 or N2 is turned on and the P-channel transistor Pl or P2 is turned off so that the output of the NOR circuit 32 will be set at the "L" level. On the other hand, when the control signal BYTE and the chip enable control signal CE* are both set at the "L" level, the P-channel transistors P1 and P2 are both turned on and the N-channel transistors N1 and N2 are both turned off so that the output of the NOR circuit 32 will be set at the "H" level.
In contrast, when a programming high potential V.sub.PP is input to the V.sub.PP power source terminal 31 in the program mode of the EPROM, the P-channel transistor P1 is turned off and the N-channel transistor N1 is turned on so that each of the drains of the P-channel transistor P1 and N-channel transistor N1, that is, an output node of the NOR circuit 32, will be set at the ground potential Vss. The operation in the program mode is effected irrespective of the "H" level/"L" level of the chip enable control signal CE*, and, at this time, the output of the NOR circuit 32 is set at the "L" level.
The "L" or "H" level output of the NOR circuit 32 in the read mode and the "L" level output of the NOR circuit 32 in the program mode are supplied as an internal signal BYTE* to an internal circuit through the two-stage amplifying inverters 33 and 34.
Since each of the drains of the P-channel transistor P1 and N-channel transistor N1 of the NOR circuit 32 is set at the ground potential Vss in the program mode and the high potential V.sub.PP is applied to each gate, an electric field stress (referred to as "stress" hereinafter) of high potential V.sub.PP is applied to each gate insulation film.
Likewise, the stress of high potential is applied to the gate insulation film of a MOS transistor to which the high potential V.sub.H of tri-state control is input in to an input-first stage circuit which is connected to a terminal for reading electric signature of the EPROM, although not shown in the drawing. The programming high potential V.sub.PP and high potential V.sub.H for tri-state control are set at 12.5 V and 12 V in the EPROMs of 1 megabits and 4 megabits, respectively.
As the elements are more miniaturized with an increase in the capacity (16 megabits, for example) of the EPROM, the thickness of the gate insulation film is subjected to the scaling and the withstanding voltage of the insulation film is lowered. In order to cope with this problem, the stress applied to the internal circuit is reduced by lowering the power source input from the exterior in the chip, without changing the external power source level. However, even when the capacity of the EPROM is increased, it is undesirable for the user that the values of the high potentials V.sub.PP and V.sub.H are subject to the scaling if the compatibilities of the devices are taken into consideration. Particularly, when the high potential V.sub.H for reading the electric signature of the EPROM is different every device, it becomes impossible to automatically specify the EPROM by means of the EPROM writer. Thus, the high potential V.sub.H for reading the signature cannot be changed. Since the high potentials V.sub.PP and V.sub.H are directly applied from the exterior device to the gates of the transistors of the input-first stage circuit which is connected to the V.sub.PP power source terminal and the address terminal for reading the signature, serious problems such as TDDB (time dependent dielectric breakdown) may occur in reliability.
The same problem as that described above may occur in an input-first stage circuit connected to a test mode terminal in a case where the circuit operates the internal test circuit to effect the reliability test etc, of the internal circuit in the test mode, by applying a high potential of tri-state control to a part of the address terminals of the EPROM or a part of the control signal input terminals to operate the internal high potential detection circuit.